The present invention relates generally to scan test, and more particularly, to a method and apparatus for generating a featured scan pattern based on test responses of a plurality of devices under test that are scan tested under stress conditions.
Nanometer scaling with its attendant process variation has made it increasingly difficult to meet quality goals in complex system-on-chip (SoC) products. For multi-million gate digital circuitry in a SoC, scan pattern count continues to rise inexorably to achieve high fault coverage targeting defects that exhibit non-stuck-at behavior, such as delay faults. Recent developments to model defects at the transistor layout level inside digital standard cells, while offering the potential to catch more defects, come at the expense of greatly increased scan pattern count. Even with continued improvements in scan compression techniques, the unrelenting technological march toward higher gate count and larger pattern size in lock-step will nonetheless chisel away at profit margins. Scan design-for-testability (DFT) has now been universally adopted for digital circuitry in SoC's. It is a major contributor to the practice of testing that has allowed high product quality to be delivered within reasonable test cost.
However, chips passing production scan patterns with high structural fault coverage may sometimes end up failing functional operation in the end-user system. Product quality suffers as indicated by a rise in defective parts per million (DPPM). Incidences of no-trouble-found when chips are returned to the supplier for diagnosis reflect the difficulty of catching subtle defects. The time to reduce initial DPPM to meet customer requirements is lengthening, working against ever shortening product life-cycles. To understand why this is happening, consider the typical large die size of current SoC's. Across the die, operating conditions can show significant local variation in terms of power level and temperature due to electrical activity. Such operating profiles can also differ significantly between test mode and functional mode where certain signal paths, say between memory and logic, are blocked to satisfy DFT compliance. The functional operating condition where a subtle defect can trigger failure may never be encountered under normal test mode conditions running production scan patterns.
To minimize defect escapes missed by scan testing, system-level testing (SLT) that mimics the end-user application can be inserted as an extra and final test step. But SLT cannot guarantee complete functional coverage and it undesirably limits high-volume throughput. SLT can help in the early production stage to identify manufacturing test holes and ensure adequate initial product quality. But it should not be a permanent part of the production test flow; and effort should be made so its role reverts to that of occasional sample monitoring. Of course even with SLT, some defects can still end up as customer in-field failures, i.e., RMA (return merchandise authorization) parts.
In view of above, there is a need to improve the traditional test flow.